PLDs are general-purpose logic devices which can be configured for various operations. Current developments in PLDs are making it possible to enhance the flexibility and complexity of these devices. Many PLDs provide complete system capabilities, including on-chip memories and a large variety and number of logic elements, that are electrically programmed for providing the desired operation by using configuration memory cells. To ensure correct implementation of functionality, it is desirable to have the ability to test the configured configuration memory cells for correctness of programming.
U.S. Pat. No. 6,237,124 describes a method for testing the configuration memory by using cyclical redundancy checking (CRC). In this technique the CRC mechanism is used to check for a single event upset (SEU) in the configuration process of the static random access memory (SRAM) of a field programmable gate array (FPGA). In one particular SRAM-based FPGA architecture described in the patent, an erasable programmable read only memory (EPROM) resides on a printed circuit board near the FPGA. This EPROM stores the configuration data for programming the configuration SRAM for the FPGA core. An EPROM controller on the FPGA directs a data stream from the EPROM into the FPGA.
The EPROM controller serializes the data stream from the EPROM into a data stream one bit wide. This data stream is synchronized to an internal clock and provides data to various portions of the FPGA architecture including control logic, row and column counters, a CRC circuit, and the configuration SRAM for the FPGA core. The CRC circuit tests the data stream from the EPROM to verify that it is correct. Also, the CRC circuit can test the data in the configuration SRAM after loading. A multiplexer selects whether the data to be checked by the CRC circuit is the input data stream or the data in the configuration SRAM. When incorrect configuration data is detected in the configuration SRAM of the FPGA core, the CRC circuit can signal the EPROM controller that an error has occurred. The EPROM controller can use this information to output an error signal from the FPGA and/or initiate a reload from the EPROM.
The configuration circuitry described above may be adequate for configuring a conventional memory array, but it includes no mechanism by which the full configuration process could be tested. For example, the CRC bits or the frame check sequence bits loaded after every frame of data make it possible to check for an error that may occur in loading the data frames in the internal shift register. Yet, the data lines themselves could be faulty with bits stuck at logic 1 or stuck at logic 0. In such a case, the data may not have correctly reached its destination, and to verify whether it was correct or not would require tracing back every bit of stored data.